The arm symbolic debugger is a front end interface to

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Unformatted text preview: will return to in Chapter 8. At its most basic, ARMsd allows an executable program to be loaded into the ARMulator or a development board and run. It allows the setting of breakpoints, which are addresses in the code that, if executed, cause execution to halt so that the processor state can be examined. In the ARMulator, or when running on hardware with appropriate support, it also allows the setting of watchpoints. These are memory addresses that, if accessed as data addresses, cause execution to halt in a similar way. At a more sophisticated level ARMsd supports full source level debugging, allowing the C programmer to debug a program using the source file to specify breakpoints and using variable names from the original program. The ARMulator (ARM emulator) is a suite of programs that models the behaviour of various ARM processor cores in software on a host system. It can operate at various levels of accuracy: The linker ARMsd ARMulator 46 The ARM Architecture Instruction-accurate modelling gives the exact behaviour of the system state without regard to the precise timing characteristics of the processor. Cycle-accurate modelling gives the exact behaviour of the processor on a cycleby-cycle basis, allowing the exact number of clock cycles that a program requires to be established. Timing-accurate modelling presents signals at the correct time within a cycle, allowing logic delays to be accounted for. All these approaches run considerably slower than the real hardware, but the first incurs the smallest speed penalty and is best suited to software development. At its simplest, the ARMulator allows an ARM program developed using the C compiler or assembler to be tested and debugged on a host machine with no ARM processor connected. It allows the number of clock cycles the program takes to execute to be measured exactly, so the performance of the target system can be evaluated. At its most complex, the ARMulator can be used as the centre of a complete, timing-accurate, C model of the target system, with full details of the cache and memory manag...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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