ARM.SoC.Architecture

The arm7 series of cpus switched to a 4 way set

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Unformatted text preview: bly requires this functionality. Embedded systems running known application code can be designed to work without memory management, and it is hard to justify the cost of the MMU for such systems. The ARM CPU cores have evolved into two distinct series, one with the full MMU for general-purpose applications and one with the much simpler memory protection unit for fixed-program embedded systems. The ARM740T and ARM940T are examples of the latter, while the general-purpose CPUs include versions that support Windows CE (ARM720T, ARM920T and ARM1020E) and those that do not (ARM? 1OT and ARMS 10). The latest development in the memory management architecture is the support for TLB lock-down in the ARMS 10, ARM920T and ARM1020E. This has a similar role to cache lock-down: it can be used to ensure that critical real-time code runs as efficiently as possible. Cache line length Memory management 346 ARM CPU Cores 12.8 Example and exercises Why is a segmented associative cache better suited to support lockdown than a set-associative cache? Early ARM CPUs, such as the ARMS whose cache was studied in Section 10.4 on page 279, used highly associative caches with a CAM-RAM structure. The ARM700 series of CPUs abandoned CAM-RAM caches in favour of RAM-RAM set-associative caches because the RAM tag store uses less die area than the equivalent CAM tag store. Later ARM CPUs, from the ARMS 10 onwards, have reverted to a CAM-RAM cache, at least in part because of the need to support partial cache lock-down. The reason why a CAM-RAM cache provides better support for lock-down is simply to do with its level of associativity. The cache locations that a particular memory location can map into are determined by decoding some of its address bits. In a direct-mapped cache there is only one cache location, a 2-way set-associative cache offers a choice of two possible locations, 4-way offers four, and so on. In the ARM CPUs that support it, lock-down operates by reducing the range of this choice. With a 4-way set-associative cache it is practical to lock down a quarter of the cache (leaving a 3-way cache), half of the cache (2-way), or three-quarte...
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