The arm920t mmu supports selective lock down for tlb

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Unformatted text preview: ead operations. The only coherency problem arises when the program that the cache holds copies of is modified in main memory. Any modification of code (such as loading a new program into memory previously occupied by a program that is no longer required) must be handled carefully, and the instruction cache selectively or completely flushed before the new program is executed. The ARM9TDMI data port supports writes as well as reads, and therefore the data cache must implement some sort of write strategy (see 'Write strategies' on page 278). The ARM946E-S and ARM966E-S 339 Table 12.6 Process Metal layers ARM940T characteristics. 802,000 MIPS 8.1 mm2 Power 0-200 MHz MIPSAV 0.25 urn Transistors 220 385 mW 3 Core area 2.5V Clock Vdd 570 As the ARM9TDMI operates at high clock rates, the data cache is designed to support write-back operation. The simpler write-through option is also available, and the memory protection unit is used to define which mode is selected for a particular address. Cache lines are allocated only on read misses. The ARM940T supports cache 'cleaning' through a software mechanism that is used to check every cache line and flush any that are dirty. This clearly takes some time. It does not have the mechanism in the ARM920T to clean lines by their memory address. ARM940T write buffer The write buffer can hold up to eight words of data and four addresses. The memory protection unit defines which addresses are bufferable. Dirty lines flushed from the data cache also pass through the write buffer. The characteristics of an ARM940T implemented on a 0.25 um CMOS process are summarized in Table 12.6 and a plot of the layout is shown in Figure 12.13 on page 340. It can be seen that the complete CPU core occupies a relatively small proportion of the area of a low-cost system-on-chip design. ARM940T silicon 12.5 The ARM946E-S and ARM966E-S The ARM946E-S and ARM966E-S are synthesizable CPU cores based upon the ARM9E-S integer core. (See 'ARM9E-S' on page 263.) Both CPU cores have AMBA AHB interfaces and can be synthesized with an embedded trace macrocell as described in Section 8.8 on page 237. They are intended for embedded applications and do not have add...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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