ARM.SoC.Architecture

The arm9tdmi pipeline is much tighter and does not

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Unformatted text preview: rn 3.3 V technology, the design has been ported onto 0.25 um and 0.18 um processes using power supplies down to 1.2 V The characteristics of the 0.25 um ARM9TDMI core when executing 32-bit ARM code are summarized in Table 9.3. A plot of the core is shown in Figure 9.8. ARM9TDMI core Figure 9.8 The ARM9TDMI processor core. ARM9TDMI applications An ARM9TDMI core has separate instruction and data memory ports. While in principle it may be possible to connect these ports to a single unified memory, in practice doing so would negate many of the reasons for choosing the ARM9TDMI core over the smaller and cheaper ARM7TDMI core in the first place. Similarly, although it is not necessary to exploit the higher clock rate supported by the ARM9TDMI's 5-stage pipeline in comparison to the ARMTTDMI's 3-stage pipeline, not to do so would negate the rationale for using the ARM9TDMI. Therefore, any application that justifies the use of an ARM9TDMI core is going to have to cope with a complex high-speed memory subsystem. ARM10TDMI 263 The most common way of handling this memory requirement will be to incorporate separate instruction and data cache memories as exemplified by the various standard ARM CPU cores based around the ARM9TDMI. The ARM920T and ARM940T CPU cores are described in Section 12.4 on page 335. The caches in these CPU cores satisfy most of the memory bandwidth requirements of the ARM9TDMI and reduce the external bandwidth requirement to something that can be satisfied by conventional unified memories connected via a single AMBA bus. An alternative solution, particularly applicable in embedded systems where the performance-critical code is relatively well contained, is to use an appropriate amount of separate directly addressed local instruction and data memory instead of caches. ARM9E-S The ARM9E-S is a synthesizable version of the ARM9TDMI core. It implements an extended version of the ARM instruction set compared with the 'hard' core. In addition to the ARM architec...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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