ARM.SoC.Architecture

The cpsr must be restored from the appropriate spsr

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Unformatted text preview: ess is in r14. To return from a SWI or undefined instruction trap use: MOVS pc, r14 To return from an IRQ, FIQ or prefetch abort use: SUBS pc, r14, #4 To return from a data abort to retry the data access use: SUBS pc, r14, #8 The 's' modifier after the opcode signifies the special form of the instruction when the destination register is the PC. Note how the return instruction incorporates an adjustment to the return address where necessary: IRQ and FIQ must return one instruction early in order to execute the instruction that was 'usurped' for the exception entry. Prefetch abort must return one instruction early to execute the instruction that had caused a memory fault when first requested. Data abort must return two instructions early to retry the data transfer instruction, which was the instruction before the one usurped for exception entry. If the handler has copied the return address out onto a stack (in order, for example, to allow re-entrant behaviour, though note that in this case the SPSR must be saved as well as the PC) the restoration of the user registers and the return may be implemented with a single multiple register transfer instruction such as: LDMFD r13!, {r0-r3,pc}" ; restore and return Here the '*' after the register list (which must include the PC) indicates that this is a special form of the instruction. The CPSR is restored at the same time that the PC is loaded from memory, which will always be the last item transferred from memory since the registers are loaded in increasing order. The stack pointer (r13) used here is the banked register belonging to the privileged operating mode; each privileged mode can have its own stack pointer which must be initialized during system start-up. Clearly the stack return mechanism can only be employed if the value in r14 was adjusted, where necessary, before being saved onto the stack. Conditional execution 111 Exception priorities Since multiple exceptions can arise at the same time it is necessary to define a priority order to determine the order in which the exceptions are handled. On ARM this is: 1. reset (highest priority); 2. data abort; 3. FIQ; 4. IRQ; 5. prefetch abort; 6. SWI, undefine...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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