ARM.SoC.Architecture

The tlb and an instruction or write through data

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Unformatted text preview: gnals. An interrupt enable register (read/write); this register controls which hardware events will generate an interrupt. A status register (read only); this register indicates whether read data is available, whether the write buffer is full, and so on. To receive data, the software must set up the device appropriately, usually to generate an interrupt when data is available or an error condition is detected. The interrupt routine must then copy the data into a buffer and check for error conditions. Memory-mapp ed issues Note that a memory-mapped peripheral register behaves differently from memory. Two consecutive reads to the read data register will probably deliver different results even though no write to that location has taken place. Whereas reads to true memory are idempotent (the read can be repeated many times, with identical results) a read to a peripheral may clear the current value and the next value may be different. Such locations are termed read-sensitive. Programs must be written very carefully where read-sensitive locations are involved, and, in particular, such locations must not be copied into a cache memory. In many ARM systems I/O locations are made inaccessible to user code, so the only way the devices can be accessed is through supervisor calls (SWIs) or through C library functions written to use those calls. Where I/O functions have a high data bandwidth, a considerable share of the processor's performance may be consumed handling interrupts from the I/O system. Many systems employ DMA hardware to handle the lowest level I/O data transfers without Direct Memory Access Input/Output 313 processor assistance. Typically, the DMA hardware will handle the transfer of blocks of data from the peripheral into a buffer area in memory, interrupting the processor only if an error occurs or when the buffer becomes full. Thus the processor sees an interrupt once per buffer rather than once per byte. Note, however, that the DMA data traffic will occupy some of th...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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