ARM.SoC.Architecture

The address of a second level coarse page descriptor

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Unformatted text preview: register 1 and the user/supervisor state of the processor to determine whether a read or write access to the addressed location is permissible. The permission checking operation proceeds as follows: 306 Architectural Support for Operating Systems Figure 11.5 Small page translation sequence. 1. If alignment checking is enabled (bit 1 of CP15 register 1 is set) check the address alignment and fault if misaligned (that is, if a word is not aligned on a 4byte boundary or a half-word is not aligned on a 2-byte boundary). 2. Identify the domain of the addressed location from bits [8:5] of the first-level descriptor. (Fetching the first-level descriptor will fault if the descriptor is invalid.) 3. Check in CP15 register 3, the domain access control register, whether the current process is a client or manager of this domain; if neither, fault here. Figure 11.6 Table 11.5 AP 00 Access permission checking scheme. Access permissions. User No access No access Read only s 0 R 0 0 Supervisor No access Read only Read only Read/write Read/write Read/write 00 00 00 01 10 1 0 1 - - 1 1 Do not use No access Read only Read/ write - - 11 308 Architectural Support for Operating Systems 4. If a manager of this domain, proceed ignoring access permissions. If a client, check the access permissions against Table 11.5 on page 307 using the S and R bits from CP15 register 1. Fault if access is not permitted, otherwise continue to access data. The permission checking scheme is illustrated in Figure 11.6 on page 307 which shows the various faults that can be generated in the course of an address translation. The MMU may generate alignment, translation, domain and permission faults. In addition, the external memory system may fault on cache line fetches (though not all CPUs support this), uncached or unbuffered accesses (aborts on buffered writes are not supported) and translation table accesses. These faults are all called aborts and are handled by the processor as prefetch or data abort exceptions, depending on whether the access was for an instruction or for data. A fault on a data access causes the fault status register (CP15 register 5) and the fault address register (CP15 register 6) to be upd...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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