ARM.SoC.Architecture

The addressing mode and auto indexing are controlled

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Unformatted text preview: s coprocessor-dependent. The use shown above is recommended and will maximize compatibility with ARM devel opment tools. 2. If the address is not word-aligned the two least significant bits will be ignored, though some ARM systems may raise an exception. 3. The number of words transferred is controlled by the coprocessor and the ARM will continue to generate sequential addresses until the coprocessor indicates that the transfer should complete (see 'Data transfers' on page 102). During the data transfer the ARM will not respond to interrupt requests, so coprocessor designers should be careful not to compromise the system interrupt response time by allow ing very long data transfers. Limiting the maximum transfer length to 16 words will ensure that coprocessor data transfers take no longer than worst-case load and store multiple register instructions. 5.19 Coprocessor register transfers These instructions allow an integer generated in a coprocessor to be transferred directly into a ARM register or the ARM condition code flags. Typical uses are: A floating-point FIX operation which returns the integer to an ARM register; A floating-point comparison which returns the result of the comparison directly to the ARM condition code flags where it can determine the control flow; A FLOAT operation which takes an integer value from an ARM register and sends it to the coprocessor where it is converted to floating-point representation and placed in a coprocessor register. The system control coprocessors used to control the cache and memory management functions on the more complex ARM CPUs (Central Processing Units) generally use these instructions to access and modify the on-chip control registers. 140 The ARM Instruction Set Binary encoding 31 Figure 5.17 Coprocessor register transfer instruction binary encoding. Description The instruction is offered to any coprocessors present; normally the coprocessor with coprocessor number CP# will accept the instruction. If no coprocessor accepts the instruction ARM ra...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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