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Unformatted text preview: -address instructions If the destination register is made implicit it is often called the accumulator (see, for example, MU0 in the previous section); an instruction need only specify one operand:
ADD s1 ; accumulator := accumulator + s1 The binary representation simplifies further to that shown in Figure 1.11. Figure 1.11 A 1-address (accumulator) instruction format. 0-address instructions Finally, an architecture may make all operand references implicit by using an evaluation stack. The assembly language format is:
ADD ; top_of_stack next_on_stack := top_of_stack + The binary representation is as shown in Figure 1.12. Figure 1.12 A 0-address instruction format. Examples of n-address use All these forms of instruction have been used in processor instruction sets apart from the 4-address form which, although it is used internally in some microcode designs, is unnecessarily expensive for a machine-level instruction set. For example: The Inmos transputer uses a 0-address evaluation stack architecture. The MU0 example in the previous section illustrates a simple 1 -address architecture. 16 An Introduction to Processor Design The Thumb instruction set used for high code density on some ARM processors uses an architecture which is predominantly of the 2-address form (see Chapter 7). The standard ARM instruction set uses a 3-address architecture. Addresses An address in the MU0 architecture is the straightforward 'absolute' address of the memory location which contains the desired operand. However, the three addresses in the ARM 3-address instruction format are register specifiers, not memory addresses. In general, the term '3-address architecture' refers to an instruction set where the two source operands and the destination can be specified independently of each other, but often only within a restricted set of possible values. We have just looked at a number of ways of specifying an 'ADD' instruction. A complete instruction set needs to do more than perform arithmetic operations on operands in memory. A general-purpose instruction set can be expected to...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09