ARM.SoC.Architecture

The base or computed address is used to load l 1 or

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Unformatted text preview: n code which is not running in user mode: setting W = 1 causes the processor to request a user mode access to memory, allowing the operating system to adopt a user view of the memory translation and protection scheme. Single word and unsigned byte data transfer instructions 127 Assembler format The pre-indexed form of the instruction: LDRlSTR{<cond>}{B} Rd, [Rn, <offset>]{!} The post-indexed form: LDRlSTR{<cond>}{B}{T} Rd, [Rn], <offset> A useful PC-relative form that leaves the assembler to do all the work: LDRlSTR{<COnd>}{B} Rd, LABEL LDR is 'load register', STR is 'store register'; the optional 'B' selects an unsigned byte transfer, the default is word; <of f set> may be # + /-<l2-bit immediate> or + /-Rm {, shift} where the shift specifier is the same as for data processing instructions except that register specified shift amounts are not available; ! selects write-back (auto-indexing) in the pre-indexed form. The T flag selects the user view of the memory translation and protection system and should only be used in non-user modes. The user should fully understand the memory management environment in which the processor is being used, so this is really only a facility for operating system experts. Examples To store a byte in r0 to a peripheral: The assembler will use a pre-indexed, PC-relative addressing mode to load the address into rl. The literal must be within range (that is, within 4 Kbytes of the load instruction) for this to be possible. Notes 1. Using the PC as the base address delivers the address of the instruction plus eight bytes; it should not be used as the offset register, nor with any auto-indexing addressing mode (including any post-indexed mode). 2. Loading a word into the PC causes a branch to the loaded address and is a recognized way of implementing jump tables. Loading a byte into the PC should be avoided. 3. Storing the PC to memory gives different results on different implementations of the processor and should therefore...
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