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Unformatted text preview: emory) will speed up exception entry. Sections of the TLB and cache can be locked down to ensure that critical code segments never incur the miss penalty. Note that even in general-purpose systems where the cache and MMU are generally beneficial there are often critical real-time constraints, for example for servicing disk data traffic or for managing the local area network. This is especially true in low-cost systems with little DMA hardware support. Other cache issues There are other things to watch out for when a cache is present, for example: Caching assumes that an address will return the same data value each time it is read until a new value is written. I/O devices do not behave like this; each time you read them they give the next piece of data. Input/Output 315 A cache fetches a block (which is typically around four words) of data at a time from sequential addresses. I/O devices often have different register functions at consecutive addresses; reading them all can give unpredictable results. Therefore the I/O area of memory is normally marked as uncacheable, and accesses bypass the cache. In general, caches interact badly with any read-sensitive devices. Display frame buffers also need careful consideration and are often made uncacheable. Operating system issues Normally, all the low-level detail of the I/O device registers and the handling of interrupts is the responsibility of the operating system. A typical process will send data to the serial port by loading the next byte into r0 and then making the appropriate supervisor call; the operating system will call a subroutine called a device driver to check for the transmit buffer being empty, that the line is active, that no transmission errors occur, and so on. There may even be a call which allows the process to pass a pointer to the operating system which will then output a complete buffer of values. Since it takes some time to send a buffer full of data down a serial line, the operating system may return control to the process until the transmit buffer...
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- Spring '09