ARM.SoC.Architecture

The caches may be locked down in 16 word units the

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Unformatted text preview: ress translation hardware. ARM946E-S cache The ARM946E-S has a 4-way set-associative cache. The set-associative organization was chosen over the CAM-RAM organization used in the ARM920T and ARM940T because it is easier to construct a set-associative cache with synthesizable RAM structures available in standard ASIC libraries. Synthesizing CAM-RAM cache structures is still difficult for most design systems. 340 ARM CPU Cores Figure 12.13 ARM940T CPU core plot. The instruction and data caches can each be from 4 Kbytes to 64 Kbytes in size, and the two caches need not be the same size as each other. Both use an 8-word line, support lock-down, and employ a software-selectable replacement algorithm which may be pseudo-random or round-robin. The write strategy is also software selectable between write-through and copy-back. The ARM946E-S incorporates memory protection units and has an overall organization similar to the ARM940T (shown in Figure 12.12 on page 338). ARM966E-S memory The ARM966E-S does not employ caches. Instead, the synthesized macrocell incorporates tightly coupled SRAM mapped to fixed memory addresses. These memories can be a range of sizes. One memory is connected only to the data port, whereas the second memory is connected to both ports. Generally the second memory is used by the instruction port, but data port access is important for two reasons: Constants (such as addresses) embedded in code must be read through the data port. There must be a mechanism for initializing the instruction memory before it can be used. The instruction port is read-only and therefore cannot be used to initialize the instruction memory. The ARM966E-S also incorporates a write buffer to optimize the use of the AMBA AHB bandwidth and supports the connection of on-chip coprocessors. TheARM1020E 341 Soft IP These synthesizable CPU cores address the strong market demand for high-performance processors that can readily be resynthesized on new process technologies. They represent an alternative to the 'hard' macrocells that have been the usual delivery mechanism for ARM technology. 12.6 TheARM1020...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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