ARM.SoC.Architecture

The core incorporates a transparent latch controlled

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Unformatted text preview: cause a mode change (note that in debug state the usual bar against switching into a privileged mode from user mode is removed). Inspecting system state is achieved by causing the ARM to access memory locations at system speed and then switch immediately back into debug state. The debug interface extends the functionality provided by the integrated EmbeddedlCE macrocell by allowing external hardware to enable debug support (via dbgen) and make an asynchronous debug request (on dbgrq) or an instruction-synchronous request (on breakpf). External hardware is informed of when the core is in debug mode via dbgack. The internal debug request signal is exported on dbgrqi. External events may contribute to the triggering of watchpoints via externO and externl, and EmbeddedlCE watchpoint matches are signalled on rangeoutO and rangeoutl. An empty communication transmission buffer is signalled on commtx, and an empty reception buffer on commrx. Debug support Debug interface 254 ARM Processor Cores The processor indicates whether or not the current instruction in the execution stage is being executed on exec. An instruction is not executed if, for example, it fails its condition code test. Coprocessor interface The cpi, cpa and cpb coprocessor interface signals were described in Section 4.5 on page 101. The additional signal provided to the coprocessors is ope, which indicates whether a memory access is to fetch an instruction or a data item. This is used by the coprocessor pipeline follower to track the ARM instruction execution. Where there is no requirement to connect a coprocessor, cpa and cpb should be tied high. This will cause all coprocessor instructions to take the undefined instruction trap. The ARM7TDMI core is designed to operate with a nominal 5 volt or 3 volt supply, though this is dependent on the capabilities of the process technology as well as the circuit design style employed in the core. The JTAG control signals are as prescribed by the standard described in Section 8.6 on page 226 and are connected to an off-chip test controller via dedicated pins. These signals are used to support the addition of further scan chains...
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