This preview shows page 1. Sign up to view the full content.
Unformatted text preview: , denning the number of cycles the sequence must take. The simplest way to view breaks in the ARM pipeline is to observe that: All instructions occupy the datapath for one or more adjacent cycles. For each cycle that an instruction occupies the datapath, it occupies the decode logic in the immediately preceding cycle. During the first datapath cycle each instruction issues a fetch for the next instruc tion but one. Branch instructions flush and refill the instruction pipeline. PC behaviour One consequence of the pipelined execution model used on the ARM is that the program counter, which is visible to the user as r!5, must run ahead of the current instruction. If, as noted above, instructions fetch the next instruction but one during their first cycle, this suggests that the PC must point eight bytes (two instructions) ahead of the current instruction. This is, indeed, what happens, and the programmer who attempts to access the PC directly through r!5 must take account of the exposure of the pipeline here. However, for most normal purposes the assembler or compiler handles all the details. Even more complex behaviour is exposed if r!5 is used later than the first cycle of an instruction, since the instruction will itself have incremented the PC during its first cycle. Such use of the PC is not often beneficial so the ARM architecture definition specifies the result as 'unpredictable' and it should be avoided, especially since later ARMs do not have the same behaviour in these cases. 4.2 5-stage pipeline ARM organization
All processors have to develop to meet the demand for higher performance. The 3-stage pipeline used in the ARM cores up to the ARM? is very cost-effective, but higher performance requires the processor organization to be rethought. The time, T , required to execute a given program is given by: where Ninst is the number of ARM instructions executed in the course of the program, CPI is the average number of clock cycles per instruction and fclk is the processor's clock frequency. Since N...
View Full Document
This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09