The data registers which hold data passing to and

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Unformatted text preview: ages: Fetch; the instruction is fetched from memory and placed in the instruction pipeline. Decode; the instruction is decoded and the datapath control signals prepared for the next cycle. In this stage the instruction 'owns' the decode logic but not the datapath. Execute; the instruction 'owns' the datapath; the register bank is read, an operand shifted, the ALU result generated and written back into a destination register. At any one time, three different instructions may occupy each of these stages, so the hardware in each stage has to be capable of independent operation. 76 ARM Organization and Implementation D[31: Figure 4.1 3-stage pipeline ARM organization. When the processor is executing simple data processing instructions the pipeline enables one instruction to be completed every clock cycle. An individual instruction takes three clock cycles to complete, so it has a three-cycle latency, but the throughput is one instruction per cycle. The 3-stage pipeline operation for single-cycle instructions is shown in Figure 4.2 on page 77. 3-stage pipeline ARM organization 77 Figure 4.2 ARM single-cycle instruction 3-stage pipeline operation. When a multi-cycle instruction is executed the flow is less regular, as illustrated in Figure 4.3. This shows a sequence of single-cycle ADD instructions with a data store instruction, STR, occurring after the first ADD. The cycles that access main memory are shown with light shading so it can be seen that memory is used in every cycle. The datapath is likewise used in every cycle, being involved in all the execute cycles, the address calculation and the data transfer. The decode logic is always generating the control signals for the datapath to use in the next cycle, so in addition to the explicit decode cycles it is also generating the control for the data transfer during the address calculation cycle of the STR. Figure 4.3 ARM multi-cycle instruction 3-stage pipeline operation. 78 ARM Organization and Implementation Thus, in this instruction sequence, all parts of the processor are active in every cycle and the memory is the limiting factor...
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