ARM.SoC.Architecture

The data which is held in the registers is under the

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Unformatted text preview: ignificant overhead in terms of the logic that is required to enable it to operate effectively. It also incurs a significant design cost if a suitable off-the-shelf cache is unavailable. It has more deterministic behaviour. Cache memories have complex behaviours which can make difficult to predict how well they will operate under particular circumstances. In particular, it can be hard to guarantee interrupt response time. The drawback with on-chip RAM vis-d-vis cache is that it requires explicit management by the programmer, whereas a cache is usually transparent to the programmer. Where the program mix is well-defined and under the control of the programmer, on-chip RAM can effectively be used as a software-controlled cache. Where the application mix cannot be predicted this control task becomes very difficult. Hence a cache is usually preferred in any general-purpose system where the application mix is unknown. One important advantage of on-chip RAM is that it enables the programmer to allocate space in it using knowledge of the future processing load. A cache left to its own devices has knowledge only of past program behaviour, and it can therefore never prepare in advance for critical future tasks. Again, this is a difference which is most likely to be significant when critical tasks must meet strict realtime constraints. The system designer must decide which is the right approach for a particular system, taking all these factors into account. Whatever form of on-chip memory is chosen, it must be specified with great care. It must be fast enough to keep the processor busy and large enough to contain critical routines, but neither too fast (or it will consume too much power) nor too large (or it will occupy too much chip area). 272 Memory Hierarchy 10.3 Caches The first RISC processors were introduced at a time when standard memory parts were faster than their contemporary microprocessors, but this situation did not persist for long. Subsequent advances in semicon...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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