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Unformatted text preview: Section 11.4 on page 297. The CPUs which use a protection unit are the ARM740T described in Section 12.1 on page 318 and the ARM940T described in Section 12.4 on page 335. ARM CPUs for use in general-purpose applications where the range and number of application programs is unknown at design time will usually require a full memory management unit with address translation. The CP15 register organization for the ARM MMU is described in Section 11.5 on page 298 and the operation of the MMU is described in Section 11.6 on page 302. CPUs which use the full MMU include all the other CPUs described in Chapter 12. MMU 11.3 CP15 protection unit registers
The protection unit register structure is illustrated in Table 11.1 on page 295. The registers are read and written using the CP15 instruction shown in Figure 11.1, with CRn specifying the register to be accessed. In detail, the register functions are as follows: CP15 protection unit registers 295 Table 11.1 Register 0 1 2 3 5 6 7 9 15 4,8,10-14 Purpose ID Register Configuration Cache Control Write Buffer Control Access Permissions Region Base and Size Cache Operations Cache Lock Down Test UNUSED CP15 protection unit register structure. Register 0 (which is read-only) returns device identification information. Bits [3:0] contain a revision number, bits [15:4] contain a 3-digit part number in binary-coded decimal, bits [23:16] contain the architecture version (0 for version 3, 1 for version 4, 2 for version 4T, 4 for version 5T) and bits [31:24] contain the ASCII code of an implementer's trademark (ASCII 'A' = 4116 indicates ARM Limited, 'D' = 44I6 indicates Digital, and so on). Some CPUs do not follow the above register 0 format exactly, and recent CPUs have a second register 0 (accessed by changing the Cop2 field in the MRC instruction) which gives details on the cache organization. Register 1 (which is read-write) contains several bits of control information which enable system functions and control system parameters. All bits are cleared on reset. If subsequently set, M enables...
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- Spring '09