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Unformatted text preview: s translates into a page, a further access is required to a second-level page table. The address of a second-level coarse page descriptor is formed by concatenating bits [31:10] of the first-level descriptor to bits [19:12] of the virtual address. The address of a second-level fine page descriptor is formed by concatenating bits [31:12] of the first-level descriptor to bits [19:10] of the virtual address. The second-level coarse page descriptor may be a large (64 Kbyte) page descriptor or a small (4 Kbyte) page descriptor, depending on its bottom two bits. '01' indicates a large page; '10' indicates a small page. Other values are trapped, and '00' should be used to generate a translation fault; '11' should not be used. A second-level fine page descriptor may also be a tiny (1 Kbyte) page descriptor, indicated by ' 11' in its bottom two bits, or it may be a large or small page descriptor as above. A small page base address is held in bits [31:12] of the page descriptor. Bits [11:4] contain two access permission bits ('APO-3') for each of the four subpages, where a subpage is a quarter of the size of the page. Bits [3:2] contain the 'bufferable' and 'cacheable' bits. (Bits marked '?' have implementation-specific uses.) ARM MMU architecture 305 Figure 11.4 Section translation sequence. The overall translation sequence for a small page is shown in Figure 11.5 on page 306. The translation sequence for a large page is similar except bits [15:12] of the virtual address are used both in the page table index and in the page offset. Each page table entry for a large page must therefore be copied 16 times in the page table for every value of these bits in the page table index. The tiny page translation scheme is also similar, but must start from a fine first-level descriptor. Tiny pages do not support subpages and therefore there is only one set of access permissions in the second-level descriptor. Access permissions The AP bits for each section or subpage are used together with the domain information in the first-level descriptor, the domain control information in CP15 register 3, the S and R control bits in CP15...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09