The mechanisms used to achieve this are called

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Unformatted text preview: g (repeating the test until it gets the 'free' result) on the lock. Note that this is the only reason for including SWAP in the ARM instruction set. It does not contribute to the processor's performance and its dynamic frequency of use is negligible. It is there just to provide this functionality. SWAP 310 Architectural Support for Operating Systems 11.8 Context switching A process runs in a context, which is all the system state that must be established for the process to run correctly. This state includes: the values of all of the processor's registers, including the program counter, stack pointer, and so on; the values in the floating-point registers, if the process uses them; the translation tables in memory (but not the contents of the TLB since it is just a cache of the values in memory and will automatically reload active values as they are used); data values used by the process in memory (but not the values in the cache since they will automatically be reloaded when required). When a process switch takes place, the context of the old process must be saved and that of the new process restored (if it is resuming rather than starting for the first time). When to switch Context switching may occur as a result of an external interrupt, for example: A timer interrupt causes the operating system to make a new process active according to a time-slicing algorithm. A high-priority process which is waiting for a particular event is reactivated in response to that event. Alternatively, a process may run out of useful work and call the operating system to be made dormant until an external event occurs. In all cases, the operating system is given or takes control and is responsible for saving the old and restoring the new context. In an ARM-based system, this will normally take place while the processor is in supervisor mode. Register state If all context switches take place in response to IRQs or internal faults or supervisor calls, and the supervisor code does not re-enable interrupts, the process register state may be restricted to the user-mode registers. If context switches may take place in response to FIQs or supervisor code...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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