ARM.SoC.Architecture

The memory data must be read and rewritten refreshed

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Unformatted text preview: eous to use cas-on\y accesses whenever possible. The difficulty is in detecting early enough in the memory access that the new address is in the same row as the previous address. Performing a comparison of the relevant bits of the new address with the corresponding bits of the previous address is almost always too slow. ARM address incrementer The solution adopted on the ARM exploits the fact that most addresses (typically 75%) are generated in the address incrementer. The ARM address selection logic (shown in Figure 8.8 on page 215) picks the address for the next cycle from one of four sources. One of these sources is the incrementer. The ARM indicates to the outside world whenever the next address is coming from the incrementer by asserting the seq output. External logic can then look at the previous address to check for row boundaries; if the previous address is not at the end of a row and the seq signal is asserted then a cas-on\y memory access can be performed. Although this mechanism will not capture all accesses which fall within the same DRAM row, it does find most of them and is very simple to implement and exploit. The seq signal and the previous address are all available over half a clock cycle before the cycle in question, giving the memory control logic plenty of time. The ARM memory interface 215 address to j signal (address + 4) Figure 8.8 ARM address register structure. A typical DRAM timing diagram is shown in Figure 8.9. The first, non-sequential access takes two clock cycles as the row address is strobed in, but subsequent sequential addresses use a cos-only access and operate in a single clock cycle. (Note that early address timing is now used, with ape or ale high.) Figure 8.9 DRAM timing illustration. The other use of the seq signal, to indicate a cycle which will use the same address as the preceding internal or coprocessor register transfer cycle, can also be exploited to improve DRAM access times. The DRAM access is started in the preceding cycle, which is only possible because seq is available...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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