ARM.SoC.Architecture

The minimal system requires 5 pins to issue pipeline

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Unformatted text preview: andwidth capacity of the trace port. If this happens, the filtering setup must be modified to reduce the amount of data that is being traced. The real-time trace technology was developed through a collaboration between ARM Limited, VLSI Technology, Inc., and Agilent Technologies (formerly part of Hewlett-Packard). VLSI Technology, Inc., offers a synthesizable version of the Embedded Trace Macrocell under the 'N-Trace' product name. The trace port analyser may be a conventional logic analyser, but an ARM-specific low-cost trace port analyser has been developed by Agilent Technologies and similar systems will become available from other vendors. The Embedded Trace Macrocell is configured via the JTAG port using software that is an extension to the ARM software development tools. The trace data is downloaded from the trace port analyser and decompressed using source code information. It is then presented as an assembly listing with interspersed data accesses, and has links back to the source code. With EmbeddedlCE and the Embedded Trace facility the ARM system-on-chip designer has all the facilities offered by traditional in-circuit emulation (ICE) tools. These technologies give full visibility of the real-time behaviour of the application code with the ability to set breakpoints and inspect and change processor registers and memory locations, always with firm links back to the high-level language source code. N-Trace Trace port analyser Trace software tools 8.9 Signal processing support Many applications that use an ARM processor as a controller also require significant digital signal processing performance. A typical GSM mobile telephone handset is a case in point; first-generation ARM-based designs typically incorporate a DSP core on the same chip as the ARM core, and the system designer has to make careful 240 Architectural Support for System Development choices regarding which system functions are best implemented on the DSP core and which on the ARM core. DSP cores have programmers' models that are very different from the ARM's model. They employ several separate data memories, and often require the programmer to schedule...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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