ARM.SoC.Architecture

The next doubling of performance achieved in the

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Unformatted text preview: efits in system-on-chip applications in that simple processors require fewer transistors than complex processors and therefore occupy less die area and consume less power. 9.6 Example and exercises How should the ARM7TDMI address bus be retimed to interface to static RAM or ROM devices? Normally the ARM7TDMI outputs new addresses as soon as they are available, which is towards the end of the preceding clock cycle. To interface to static memory devices the address must be held stable until after the end of the cycle, so this pipelining must be removed. This is most simply achieved by using ape, the address pipeline enable signal. In systems where some memory devices benefit from early addresses and some are static, either an external latch should be used to retime the addresses to the static devices or ape should be controlled to suit the currently addressed device. Review the processor cores described in this chapter and discuss the basic techniques used to increase the core performance by a factor of eight in going from the ARM7TDMI to the ARM10TDMI. Example 9.1 Exercise 9.1.1 268 ARM Processor Cores Exercise 9.1.2 In a system where the designer is free to vary the supply voltage to the processor it is possible to trade off performance (which scales in proportion to Vdd) against power-efficiency (which scales as 1/Vdd2). A measure of architectural power-efficiency that factors out the effect of power supply variations is therefore MIP3/W. Compare each of the processor cores presented here on the basis of this measure. Following on from the results of the previous exercise, why might the designer of a low-power system not simply select the most architecturally efficient processor core and then scale the supply voltage to give the required system performance? Exercise 9.1.3 Memory Hierarchy Summary of chapter contents A modern microprocessor can execute instructions at a very high rate. To exploit this potential performance fully the processor must be connected to a memory system which is both very larg...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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