The normal organization of the test circuit on a

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: be employed on the chip to test other functions as required. Data registers Instructions The normal operation of a JTAG test system is to enter an instruction which specifies the sort of test to be carried out next and the data register to be used for that test into the instruction register, and then to use the data register to carry out the test. Instructions may be public or private. Public instructions are declared and available for general test use, and the standard specifies a minimum set of public instructions 228 Architectural Support for System Development Figure 8.15 Test Access Port (TAP) controller state transition diagram. that must be supported by all devices that comply with the standard. Private instructions are for specialized on-chip test purposes and the standard does not specify how these should operate or how they should be used. Public instructions The minimum set of public instructions that all compliant devices must support is: BYPASS: here the device connects TDIto TOO though a single clock delay. This instruction exists to facilitate the testing of other devices in the same test loop. The JTAG boundary scan test architecture 229 EXTEST: here the boundary scan register is connected between TDI and TOO and the pin states are captured and controlled by the register. Referring to the state transition diagram in Figure 8.15 on page 228, the pin states are captured in the Capture DR state and shifted out of the register via the TDO pin in the Shift DR state. As the captured data is shifted out, new data is shifted in via the TDI pin, and this data is applied to the boundary scan register outputs (and hence the output pins) in the Update DR state. This instruction exists to support the testing of board-level connectivity. IDCODE: here the ID register is connected between TDI and TDO. In the Capture DR state the device ID (a hard-wired identification number giving the manufacturer, part number and version of the part) is copied into the register which is then shifted out in the Shift DR state. Other public...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online