The organization of the arm740t is illustrated in

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ARM810 is illustrated in Figure 12.5 on page 325. Double-ba ndwidth cache The core's double-bandwidth requirement is satisfied by the cache; external memory accesses use conventional line refill and individual data transfer protocols. Double-bandwidth is available from the cache only for sequential memory accesses, so it is exploited by the prefetch unit for instruction fetches and by the core for load multiple register instructions. Since the pipeline organization used on ARM7TDMI uses the memory interface almost every cycle, some way must be found to increase the available memory bandwidth if the CPI (the number of clocks per instruction) of the processor is to be The ARM810 325 improved. The StrongARM (described in the next section) achieves an increased bandwidth by incorporating separate instruction and data caches, thereby making double the bandwidth potentially available (though not all of this bandwidth can be used since the ARM generates instruction traffic with around twice the bandwidth of the data traffic, so the effective increase in bandwidth is approximately 50%). The ARMS 10 delivers an increased bandwidth by returning two sequential words per clock cycle which, since typically around 75% of an ARM's memory accesses are sequential, increases the usable bandwidth by about 60%. Although the ARMS 10 approach gives more bandwidth, it also creates more opportunity for conflict between instruction and data accesses; evaluating the relative merits of the two approaches is not straightforward. As the cache uses a copy-back write strategy and is virtually addressed, evicting a dirty line requires an address translation. The mechanism used on the ARMS 10 is to send the virtual tag to the MMU for translation. 326 ARM CPU Cores Figure 12.6 ARM810 die photograph. ARM810 silicon A photograph of an ARM810 die is shown in Figure 12.6. The ARMS core datapath is visible at the top of the photograph with its control logic immediately below. The MMU TLB is in the top right-hand corn...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online