ARM.SoC.Architecture

ARM.SoC.Architecture

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: age 226) is considered part of the processor macrocell. Hardware interface The ARM7TDMI hardware interface signals are shown in Figure 9.2 on page 250. The apparently bewildering number of signals is rather misleading as it suggests a ARM7TDMI 249 Figure 9.1 ARM7TDMI organization. complexity of behaviour that belies the intrinsic simplicity of the basic ARM interface. Numerically the interface signals are dominated by the principal 32-bit address and data buses, and a simple memory interface will use these and a few control signals as described below. The other signals are dedicated to more esoteric functions such as on-chip debug, JTAG boundary scan extensions, and so on. In Figure 9.2 on page 250 the interface signals are shown grouped by function, and the role of each group is described below with, where appropriate, information on the individual signals and the interface timing. Clock control All state changes within the processor are controlled by mclk, the memory clock. Although this clock may be manipulated externally to cause the processor to wait for a slow access, it is often simpler to supply a free-running clock and to use wait to skip clock cycles. The internal clock is effectively just a logical AND of mclk and wait, so wait must only change when mclk is low. The eclh clock output reflects the clock used by the core, so it normally reflects the behaviour of mclk after wait has been gated in, but it also reflects the behaviour of the debug clock when in debugging mode. The memory interface comprises the 32-bit address (A[31:OJ), a bidirectional data bus (D[31:OJ), separate data out (Dout[31:OJ) and data in (Din[31:OJ) buses together with ten control signals. mreq indicates a processor cycle which requires a memory access. seq indicates that the memory address will be sequential to (or possibly the same as) that used in the previous cycle. Memory interface Figure 9.2 The ARM7TDMI core interface signals. lock indicates that the processor should keep the bus to ensure the atomicity of the read and write phases of a SWAP instruction. r/w indicates whether the processor is performing a read or a write...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online