The permission checking operation proceeds as follows

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Unformatted text preview: ated to provide information on the cause and location of the fault. A fault on an instruction access only causes an exception if and when the instruction is executed (it may not be executed since it may be fetched just after a taken branch), and it does not update the fault status and address registers. The fault address may be deduced from the return address in the link register. Cache and write buffer control The C and B bits in the section and second-level page descriptors control whether the data in the section or page may be copied into a cache and/or written back to memory through a write buffer. Where the cache uses a write-through scheme, C controls whether or not the data is cacheable and B controls whether or not writes may be buffered. Where the cache uses a copy-back scheme the 'cached, unbuffered' combination may alternatively be used to specify a 'write-through, buffered' behaviour. (This cache terminology is described in 'Write strategies' on page 278.) Note that the processor cannot recover from external faults signalled on buffered writes, because by the time the fault is signalled the processor may have executed several instructions and is therefore unable to recover its state to retry the faulting store instruction. Where recovery is required (for example, to allow the processor to retry a store instruction following a bus fault) unbuffered writes must be used. In typical ARM applications there are no potentially recoverable sources of external faults, so this is not an issue. External faults Synchronization 309 11.7 Synchronization A standard problem in a system which runs multiple processes that share data structures is to control accesses to the shared data to ensure correct behaviour. For example, consider a system where a set of sensor values is sampled and stored in memory by one process and used at arbitrary times by another. If it is important that the second process always sees a single snapshot of the values, care must be taken to ensure that the first process does not get swapped out and the second swapped in when the values are only partially updated. The mechanisms used to achieve this...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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