The privileged modes can only be entered through

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Unformatted text preview: is to be re-entrant (for example, if supervisor code makes supervisor calls to itself) then the SPSR must be copied into a general register and saved. 5.2 Exceptions Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults. In the ARM architecture the term is also used to cover software interrupts and undefined instruction traps (which do not really qualify as 'unexpected') and the system reset function which logically arises before rather than during the execution of a program (although the processor may be reset again while running). These events are all grouped under the 'exception' heading because they all use the same basic mechanism within the processor. ARM exceptions may be considered in three groups: 1. Exceptions generated as the direct effect of executing an instruction. Software interrupts, undefined instructions (including coprocessor instructions where the requested coprocessor is absent) and prefetch aborts (instructions that are invalid due to a memory fault occurring during fetch) come under this heading. 2. Exceptions generated as a side-effect of an instruction. Data aborts (a memory fault during a load or store data access) are in this class. 3. Exceptions generated externally, unrelated to the instruction flow. Reset, IRQ and FIQ fall into this category. Exceptions 109 Exception entry When an exception arises, ARM completes the current instruction as best it can (except that reset exceptions terminate the current instruction immediately) and then departs from the current instruction sequence to handle the exception. Exception entry caused by a side-effect or an external event usurps the next instruction in the current sequence; direct-effect exceptions are handled in sequence as they arise. The processor performs the following sequence of actions: It changes to the operating mode corresponding to the particular exception. It saves the address of the instruction following the exception entry instruction in r14 of the new mode. It saves the old value of the CPSR in...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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