ARM.SoC.Architecture

The processor can still support virtual memory since

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Unformatted text preview: illustrated in Figure 12.4 on page 324. ARM740T silicon The characteristics of an ARM740T implemented on a 0.35 um CMOS process are summarized in Table 12.2. As can be seen from Table 12.2, the general characteristics of the ARM740T are the same as those of the ARM710T and 720T as listed in Table 12.1 on page 322. The only significant differences are the saving of just under 2 mm2 of core area due to the omission of the MMU, and the reduced power consumption. Table 12.2 ARM740T characteristics. Process Metal layers 0.35 um Transistors N/A MIPS 9.8 mm2 Power 0-59 MHz MIPS/W 53 175 mW 3 Core area 3.3V Clock Vdd 300 12.2 TheARMSIO The ARMS 10 is a high-performance ARM CPU chip with an on-chip cache and memory management unit. It was the first implementation of the ARM instruction set developed by ARM Limited to use a fundamentally different pipeline structure from that used on the original ARM chip designed at Acorn Computers and carried through to ARM6 and ARM7. The ARMS 10 has now been superseded by the ARM9 series. The ARMS core is the integer processing unit used in the ARMS 10. It was described in Section 9.2 on page 256. The ARMS 10 adds the following on-chip support to the basic CPU: An 8 Kbyte virtually addressed unified instruction and data cache using a copy-back (or write-through, controlled by the page table entry) write strategy and offering a double-bandwidth capability as required by the ARMS core. The cache is 64-way associative, and constructed from 1 Kbyte components to simplify the future development of a smaller cache for an embedded system chip or a larger cache on a more advanced process technology. It is designed so that areas of the 324 ARM CPU Cores Figure 12.4 ARM740T organization. cache can be 'locked down' to ensure that speed-critical sections of code, which arise in many embedded applications, do not get flushed. A memory management unit conforming to the ARM MMU architecture described in Section 11.6 on page 302 using the system control coprocessor described in Section 11.5 on page 298. A write buffer to allow the processor to continue while the write to external memory completes. The organization of the...
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