The reorder buffer accepts results from the execution

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Unformatted text preview: onale for self-timing The decision to employ a self-timed processing subsystem in the DRACO chip was influenced primarily by the electromagnetic compatibility (EMC) advantages of self-timed logic. The radio interference generated by high-speed clocked systems can compromise the performance of the DECT radio communication; a harmonic of the clock is likely to fall within one of the DECT channel frequency bands, possibly rendering that channel unusable. The logical conclusion might be to make all of the chip operate in self-timed logic. However, many of the telecommunications interfaces are intrinsically highly synchronous and are much easier to design using synchronous synthesis tools. The synchronous peripheral subsystem should not compromise the EMC advantages offered by the self-timed processing subsystem since the characteristic frequencies of the peripherals are all much lower than the processing rate. All the high-speed processing and the heavily loaded external memory bus operate asynchro-nously, giving most of the advantages of a fully self-timed system without incurring the design cost of developing self-timed telecommunications peripherals. The DRACO chip includes the following functions in the synchronous peripheral subsystem: an ISDN controller with a 16 Kbit/s HDLC controller and transformerless ana logue ISDN interfaces; a DECT radio interface baseband controller and analogue interface to the DECT radio subsystem; a DECT encryption engine; a four-channel full-duplex ADPCM/PCM conversion signal processor; 8 Kbytes of shared RAM used for buffer space by the DECT controller; a telecommunications codec with an analogue front-end for speech input and output which could alternatively be used for an analogue telecommunications port; two high-speed UARTs with an IrDA interface that can be used by either UART; an interrupt controller; counter-timers and a watchdog timer; a 2 Mbit/s IOM2 highway controller with programmable switching functionality; an I2C interface; an analogue-to-digital converter (ADC) interface; 65 flexible I/O ports including...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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