ARM.SoC.Architecture

The rest of the virtual address is presented to the

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Unformatted text preview: e fast clock. Depending on whether or not the addressed data is found in the cache, the processor can proceed in one of the following ways: So long as the address is non-sequential, does not fault in the MMU and is either a read found in the cache or a buffered write, the state machine remains in the Check tag state and a data value is returned or written every clock cycle. When the next address is a sequential read in the same cache line or a sequential buffered write, the state machine moves to the Sequential fast state where the data may be accessed without checking the tag and without activating the MMU. This saves power, and exploits the seq signal from the processor core. Again a data value is read or written every clock cycle. If the address is not in the cache or is an unbuffered write an external access is required. This begins in the Start external state. Reads from uncacheable memory and unbuffered writes are completed as single memory transactions in the Exter nal state. Cacheable reads perform a quad-word line fetch, after fetching the nec essary translation information if this was not already in the MMU. Cycles where the processor does not use memory are executed in the Idle state. At several points in the translation process it may become clear that the access cannot be completed and the Abort state is entered. Uncacheable reads and unbuffered writes may also be aborted by external hardware. 10.5 Memory management Modern computer systems typically have many programs active at the same time. A single processor can, of course, only execute instructions from one program at any instant, but by switching rapidly between the active programs they all appear to be executing at once, at least when viewed on a human timescale. 284 Memory Hierarchy 1 MMU hit section OK Figure 10.9 ARM600 cache control state machine. The rapid switching is managed by the operating system, so the application programmer can write his or her program as though it owns the whole machine. The mechanism used to support this illusion is described by the term memory management unit (MMU). There are two principal approaches to memory management, called segmentation and paging. Segments The simplest form of memory management allow...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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