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Unformatted text preview: from standard memory parts. The efficiency of the memory interface is an important determinant of the system performance, so these principles must be well understood by the designer who wishes to develop a high-performance system. More recent ARM cores have direct AMBA interfaces (see Section 8.2 on page 216), but many of the basic issues discussed here still apply. ARM bus signals ARM processor chips vary in the details of their bus interfaces, but they are generally similar in nature. The memory bus interface signals include the following: A 32-bit address bus, A[31:0], which gives the byte address of the data to be accessed. A 32-bit bidirectional data bus, D[3J:OJ, along which the data is transferred. Signals that specify whether the memory is needed (mreq) and whether the address is sequential (seq); these are issued in the previous cycle so that the memory control logic can prepare appropriately. Signals that specify the direction (r/w) and size (b/w on earlier processors; mas[1:0] on later processors) of the transfer. Bus timing and control signals (abe, ale, ape, dbe, lock, bl[3:0]). Simple memory interface The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM). These devices require the address to be stable until the end of the cycle, which may be achieved by disabling the address pipeline (tying ape low) on later processors or retiming the address bus (connecting ale to mclk) on earlier processors. The address and data buses may then be connected directly to the memory parts as shown in Figure 8.1 on page 209 which also shows the output enable signals (RAMoe and ROMoe) and the write enables (RAMwe). This figure illustrates the connection of 8-bit memory parts, which are a standard configuration for SRAMs and ROMs. Four parts of each type are required to form a 32-bit memory and an individual device is connected to a single byte section of the bus. The notation on the figure shows the device's bus numbering inside the device and the bus wires to which it is connected outside the device, so, for example, the SRAM shown nearest the ARM has its pins D[7:0] connected to b...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09