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Unformatted text preview: miss, the cache can continue to satisfy subsequent data references (provided that they don't also miss) while it is fetching the line containing the missing data. Hit-under-miss buffer 342 ARM CPU Cores ARM1020E write 64buffer The write buffer comprises eight slots each capable of holding an address and a bit data double-word. A separate four-slot write buffer is used to handle cache castouts to ensure that there is no conflict in the main write buffer between cast-outs and hit-under-miss write traffic. The memory management systems is based upon two 64-entry translation look-aside buffers, one for each cache. The TLBs also support selective lock-down to ensure that translation entries for critical real-time code sections do not get ejected. The external memory bus interface is AMBA AHB compliant (see Section 8.2 on page 216). The ARM1020E has separate AMBA AHB interfaces for the instruction and data memories. Each interface makes its own requests to the bus arbiter, though they share the 32-bit address and 64-bit unidirectional read and write data bus interfaces. The target characteristics for an ARM1020E running at 1.5 V on 0.18 urn CMOS are summarized in Table 12.7. The CPU will run at supply voltages down to 1.2 V for improved power-efficiency.
Table 12.7 ARM 1020E target characteristics. 7,000,000 MIPS 12mm2 Power 0-400 MHz MIPS/W 500 400 mW 1,250 ARM1020E MMU ARM1020Ebus interface ARM1020E silicon Process Metal layers Vdd 0.18 urn Transistors 5 Core area 1.5V Clock ARM10200 The ARM 10200 is a reference chip design based upon the ARM1020E CPU core, to which the following additions have been made: a VFP10 vector floatingpoint unit; a high-performance synchronous DRAM interface; a phase-locked loop circuit to generate the high-speed CPU clock. The ARM 10200 is intended to be used for the evaluation of the ARM1020E CPU core and to support benchmarking and system prototyping activities. VFP10 High-performance vector floating-point support is provided for the ARM10TDMI through the accompanying VFP 10 floating-point coprocesso...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.
- Spring '09