ARM.SoC.Architecture

There is therefore a trade off to be struck between

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Unformatted text preview: ower to the point where is becomes comparable with the dynamic power, and therefore leakage power must be taken into consideration when selecting packaging and cooling systems. To conclude this introduction to design techniques for low power consumption, here are some suggested strategies for low-power applications. Minimize Vdd. Choose the lowest clock frequency that delivers the required performance, then set the power supply voltage as low as is practical given the clock frequency and the requirements of the various system components. Be wary of reducing the supply voltage so far that leakage compromises standby power. Minimize off-chip activity. Off-chip capacitances are much higher than on-chip loads, so always minimize off-chip activity. Avoid allowing transients to drive off-chip loads and use caches to minimize accesses to off-chip memories. Minimize on-chip activity. Lower priority than minimizing off-chip activity, it is still important to avoid clocking unnecessary circuit functions (for example, by using gated clocks) and to employ sleep modes where possible. 32 An Introduction to Processor Design Exploit parallelism. Where the power supply voltage is a free variable parallelism can be exploited to improve power-efficiency. Duplicating a circuit allows the two circuits to sustain the same performance at half the clock frequency of the original circuit, which allows the required performance to be delivered with a lower supply voltage. Design for low power is an active research area and one where new ideas are being generated at a high rate. It is expected that a combination of process and design technology improvements will yield considerable further improvement in the power-efficiency of high-speed digital circuits over the next decade. 1.8 Examples and exercises (The more practical exercises will require you to have access to some form of hardware simulation environment.) Example 1.1 Design a 4-bit binary counter using logic gates and a 4-bit register. If the register inputs are denoted by D[0] to D[3] and its outputs are denoted by Q[0] to Q[3], the counter may be implemented by building combinatorial logic th...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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