ARM.SoC.Architecture

Therefore it is likely that some debugging of the

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Unformatted text preview: e chip from further pressure. JTAG scan chains are used to access the breakpoint and watch-point registers and also to force instructions into the processor to access processor and system state. The breakpoint and watchpoint registers represent a fairly small hardware overhead that can often be accepted on production parts. The host system runs the standard ARM development tools, communicating with the target through a serial port and/or a parallel port. Special protocol conversion hardware sits between the host serial line and the target JTAG port. In addition to the breakpoint and watchpoint events, it may also be desirable to halt the processor when a system-level event occurs. The debug architecture includes external inputs for this purpose. The on-chip cell containing these facilities is called the EmbeddedlCE module. Embedded-ICE The EmbeddedlCE module consists of two watchpoint registers and control and status registers. The watchpoint registers can halt the ARM core when the address, data and control signals match the value programmed into the watchpoint register. Since the comparison is performed under a mask, either watchpoint register can be configured to operate as a breakpoint register capable of halting the processor when an instruction in either ROM or RAM is executed. The comparison and mask logic is illustrated in Figure 8.17. Figure 8.17 EmbeddedlCE signal comparison logic. The ARM debug architecture 235 Chaining Each watchpoint can look for a particular combination of values on the ARM address bus, data bus, trans, ope, mo?[l:0] and r/w control signals, and if either combination is matched the processor is stopped. Alternatively, the two watchpoints may be chained to halt the processor when the second watchpoint is matched only after the first has previously been matched. EmbeddedlCE registers are programmed via the JTAG test port, using a dedicated scan chain. The scan chain is 38 bits long, with 32 data bits, 5 address bits and a r/w bit which controls whether t...
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