ARM.SoC.Architecture

These are the only bits that may be updated by user

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: enable settings. The particular case illustrated could be simplified since IRQ mode just requires one bit cleared from supervisor mode (see Table 5.1 on page 108), but the code above can be used to move between any two non-user modes or from a non-user mode into user mode. The mode change takes effect only after the MSR has been executed; the intermediate working has no effect on the mode until the result is copied back into the CPSR. 136 The ARM Instruction Set Notes 1. Attempts to modify any of CPSR[23:0] whilst in user mode have no effect. 2. Attempts to access the SPSR whilst in user or system mode should be avoided, since they have unpredictable results as there is no SPSR in these modes. 5.16 Coprocessor instructions The ARM architecture supports a general mechanism for extending the instruction set through the addition of coprocessors. The most common use of a coprocessor is the system coprocessor used to control on-chip functions such as the cache and memory management unit on the ARM720. A floating-point ARM coprocessor has also been developed, and application-specific coprocessors are a possibility. Coprocessor registers ARM coprocessors have their own private register sets and their state is controlled by instructions that mirror the instructions that control ARM registers. The ARM has sole responsibility for control flow, so the coprocessor instructions are concerned with data processing and data transfer. Following RISC load-store architectural principles, these categories are cleanly separated. The instruction formats reflect this: Coprocessor data operations are completely internal to the coprocessor and cause a state change in the coprocessor registers. An example would be floating-point addition, where two registers in the floating-point coprocessor are added together and the result placed into a third register. Coprocessor data transfer instructions load or store the values in coprocessor reg isters from or to memory. Since coprocessors may support their own data types,...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online