ARM.SoC.Architecture

These make interfacing memories which are less than

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Unformatted text preview: fferent translation tables can be used for user and supervisor code (though this is rarely done). Where more detailed information about the operating mode is required, mode[4:0] reflects the bottom five bits of the CPSR (inverted), though memory management at this level is rarely used; the detailed mode information is probably of most use when debugging. 252 ARM Processor Cores Figure 9.3 ARM7TDMI core memory and MMU interface timing. Where an access is disallowed, this is signalled on the abort input. The timing of abort is such that it must be valid at the end of the cycle, with the data. This is illustrated in Figure 9.3. An aborted memory access causes the processor to take a prefetch or data abort, depending on the value of ope during the access. The MMU may also use the ope signal where it is desired to support execute-only areas of memory, but it should be noted that this precludes the use of literal pools held in the code area for PC-relative access. For this reason execute-only protection is not widely used in ARM systems (and, in particular, is not supported in the ARM MMU architecture described in Section 11.6 on page 302). State The Tbit output tells the environment whether the processor is currently executing ARM or Thumb instructions. bigend switches the byte ordering between little- and big-endian (see 'Memory organization' on page 106 for an explanation of endianness). This input configures the way the processor operates and is not expected to change dynamically, although it can be changed during phase 2 of the clock if necessary. The two interrupt inputs may be asynchronous to the processor clock since they pass through synchronizing latches before entering the processor's control logic. The fast interrupt request,^, has higher priority than the normal interrupt request, irq. The isync input allows the interrupt synchronizers to be bypassed when the environment supplies inputs that are already synchronous to mclk', this removes the synchronizing delay...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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