ARM.SoC.Architecture

They therefore give efficient access to values held

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Unformatted text preview: to the 64-bit value in RdHi:RdLo, and the result placed in RdHi:RdLo. SMULxy{cond} Rd,Rm,Rs ; mul 11, Rn = 0 This instruction computes the 16 x 16 product of the two signed 16-bit values from the lower (x = 0) or upper (x = 1) half of Rm and the lower (y = 0) or upper (y = 1) half of Rs. The 32-bit product is placed in Rd. In all the above instructions the CPSR flags N, Z, C and V are not affected by the instruction, and the PC (r15) should not be used for any of the operand or result registers. If the addition in the accumulation (in SMLA and SMLAW) overflows the Q bit in the CPSR is set, but the addition uses conventional modulo 232 rather than saturating arithmetic. V5TE add/ SUbtract instructions The other group of instructions in the architecture v5TE extensions are 32-bit addition and subtraction instructions that use saturating arithmetic. In each case there is an additional instruction which also doubles one of the operands before performing the addition and subtraction, which improves the efficiency of certain signal processing algorithms. The binary encoding of these instructions is shown in Figure 8.23. Figure 8.23 Architecture v5TE add/subtract instruction binary encoding. The instructions supported by this format are: QADD{cond} Rd,Rm,Rn ; op = 00 This instruction performs a 32-bit saturating addition of Rm and Rn, placing the result in Rd. 244 Architectural Support for System Development QSUB{cond} Rd,Rm,Rn ; = op 01 This instruction performs a 32-bit saturating subtraction of Rn from Rm, placing the result in Rd. QDADD{cond} Rd,Rm,Rn ; op 10 = This instruction doubles Rn (with saturation) and then performs a 32-bit saturating addition of the result and Rm, placing the result in Rd. QDSUB{cond) Rd,Rm,Rn ; = op 11 This instruction doubles Rn (with saturation) and then performs a 32-bit saturating subtraction of the result from Rm, placing the result in Rd. Again, in all the above instructions the CPSR flags N, Z, C and V are not affected by the instruction, and the PC (r!5) should not be used for...
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