ARM.SoC.Architecture

This can enable some memory devices to operate at

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Unformatted text preview: ransfer the data from there to the destination register. Branch instructions Branch instructions compute the target address in the first cycle as shown in Figure 4.7 on page 85. A 24-bit immediate field is extracted from the instruction and then shifted left two bit positions to give a word-aligned offset which is added to the PC. The result is issued as an instruction fetch address, and while the instruction pipeline refills the return address is copied into the link register (r14) if this is required (that is, if the instruction is a 'branch with link'). ARM instruction execution 85 Figure 4.7 The first two (of three) cycles of a branch instruction. The third cycle, which is required to complete the pipeline refilling, is also used to make a small correction to the value stored in the link register in order that it points directly at the instruction which follows the branch. This is necessary because r15 contains pc + 8 whereas the address of the next instruction is pc + 4 (see 'PC behaviour' on page 78). Other ARM instructions operate in a similar manner to those described above. We will now move on to look in more detail at how the datapath carries out these operations. 86 ARM Organization and Implementation 4.4 ARM implementation The ARM implementation follows a similar approach to that outlined in Chapter 1 for MU0; the design is divided into a datapath section that is described in register transfer level (RTL) notation and a control section that is viewed as a finite state machine (FSM). Clocking scheme Unlike the MU0 example presented in Section 1.3 on page 7, most ARMs do not operate with edge-sensitive registers; instead the design is based around 2-phase non-overlapping clocks, as shown in Figure 4.8, which are generated internally from a single input clock signal. This scheme allows the use of level-sensitive transparent latches. Data movement is controlled by passing the data alternately through latches which are open during phase 1 and latches which are open during phase 2. The non-over...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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