This minimizes the pollution of the data cache with

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: issue unit (IBOX) and the execution unit (EBOX) with high-speed multiplication hardware (MUL). The write buffer and external bus controller complete the processor logic. StrongARM SJlicon Figure 12.10 StrongARM die photograph. The ARM920T and ARM940T 335 The high-frequency on-chip clock is generated by a phase-locked loop (PLL) from an external 3.68 MHz clock input. The characteristics of the StrongARM are summarized in Table 12.4. Table 12.4 StrongARM characteristics. 12.4 The ARM920T and ARM940T The ARM920T and ARM940T are based upon the ARM9TDMI processor core (see Section 9.3 on page 260), to which instruction and data caches have been added. The instruction and data ports are merged via an AMBA bus master unit, and a write buffer and memory management unit (ARM920T) or memory protection unit (ARM940T) are also incorporated. ARM920T ARM920T caches The overall organization of the ARM920T is illustrated in Figure 12.11 on page 336. The instruction and data caches are both 16 Kbytes in size and are built using a segmented CAM-RAM organization to give 64-way associativity. Each cache comprises eight segments of 64 lines, the required segment being addressed by A[7:5]. They have 8-word (32 byte) lines and support lock-down in units of 256 bytes (corresponding to one line in each segment). The replacement strategy is pseudo-random or round-robin, and is determined by the 'RR' bit (bit 14) in CP15 register 1. A complete 8-word line is reloaded on a cache miss. The instruction cache is read-only. The data cache supports a copy-back write strategy, and each line has one valid bit, two dirty bits and a write-back bit. The write-back bit duplicates information usually found in the translation system, and enables the cache to implement a write operation as write-through or copy-back without reference to the MMU. When a cache line is replaced any dirty data is sent to the write buffer, and this may amount to zero, four or eight words depending on the two dirty bits. The dat...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online