ARM.SoC.Architecture

To compensate the arm7500fe has a half size cache but

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Unformatted text preview: troller; a real-time clock that runs from a 32 KHz crystal source; 28 general-purpose I/O pins. Peripherals The peripheral subsystem includes an LCD controller and specialized serial ports for USB, SDLC, IrDA, codec and standard UART functions. A 6-channel DMA controller releases the CPU from straightforward data transfer responsibilities. As can be seen from Figure 13.16, the SA-1100 is built around two buses connected through a bridge: The system bus connects all the bus masters and the off-chip memory. The peripheral bus connects all the slave peripheral devices. This dual bus structure is similar to the AMBA ASB-APB (or AHB-APB) split. It minimizes the size of the bus that has a high duty cycle and also reduces the complexity and cost of the bus interface that must be built into all of the peripherals. Bus structure Applications A typical SA-1100 application will require a certain amount of off-chip memory, probably including some DRAM and some ROM and/or flash memory. All that is then required is the necessary interface electronics for the various peripheral interfaces, display, and so on. The resulting system is very simple at the PCB level, yet very powerful and sophisticated in terms of its processing capability and system architecture. The characteristics of the SA-1100 chip are summarized in Table 13.4 and a plot of the die is shown in Figure 13.17 on page 371. The chip can operate with a power supply voltage as low as 1.5V for optimum power-efficiency. Higher performance can be achieved at the cost of somewhat lower power-efficiency by operating the device at a slightly higher supply voltage. Table 13.4 SA-1100 characteristics. 2,500,000 MIPS 75mm2 Power 190/220 MHz MIPS/W 220/250 330/550 mW 665/450 SA-1100 silicon Process Metal layers Vdd 0.35 um Transistors 3 Die area 1.5/2V Clock Examples and exercises 371 Figure 13.17 SA-1100 die plot. 13.8 Examples and exercises Estimate the performance improvement which results from running a critical DSP routine in zero wait state on-chip RAM instead of two wait state off-chip RAM. Typical DS...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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