ARM.SoC.Architecture

To reap the benefits of asynchronous operation the

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Unformatted text preview: for the other to complete. Conflicts (and average memory access times) are further reduced by including separate quad-word instruction and data buffers in each RAM block. Each access to a block first checks to see whether the required data is in the buffer. Only if it is not must the RAM be interrogated, with a risk of conflict. Simulations suggest that about 60% of instruction fetches may be satisfied from within these buffers and many short, time-critical loops will run entirely from them. These buffers, in effect, form simple 128-byte first-level caches in front of the RAM blocks. This is a particularly apt analogy when it is observed that the avoidance of the RAM array results in a faster read cycle, an occurrence which is accepted automatically by the asynchronous pipeline. Test interface controller AMULET3H is being developed for commercial use and must therefore be testable in production. There are many features in the design to ensure that this is possible, the most visible of which is the test interface controller (see Figure 14.12 on page 393). This extension to the external memory interface logic follows the example set by AMBA (see "Test interface" on page 219) in enabling the external memory interface, which in normal operation is a MARBLE slave, to become a MARBLE master for test purposes. In test mode production test equipment can become a MARBLE master, allowing it to read on-chip ROM and to read and write on-chip RAM, and to access the many other test facilities built into the AMULET3H system, all of which are controlled via test registers connected to the MARBLE bus. The DRACO telecommunications controller 395 AMULET3H performance The simulated performance characteristics of the AMULET3H subsystem are summarized in Table 14.5. (The transistor count, area and power figures are for the asynchronous subsystem only. Overall the DRACO die is 7.8 x 7.3 mm.) The maximum system performance is slightly lower than that of the AMULET3 core (reported in Table 14.4 on page 390) since the on-chip RAM cannot supply the processor's peak instruction bandwidth requirement. The system power-efficiency is lower than that o...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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