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Unformatted text preview: humb code extends this advantage to give ARM better code density than most CISC processors. The ARM instruction set The I/O system The ARM handles I/O (input/output) peripherals (such as disk controllers, network interfaces, and so on) as memory-mapped devices with interrupt support. The internal registers in these devices appear as addressable locations within the ARM's ARM development tools 43 memory map and may be read and written using the same (load-store) instructions as any other memory locations. Peripherals may attract the processor's attention by making an interrupt request using either the normal interrupt (IRQ) or the fast interrupt (FIQ) input. Both interrupt inputs are level-sensitive and maskable. Normally most interrupt sources share the IRQ input, with just one or two time-critical sources connected to the higher-priority FIQ input. Some systems may include direct memory access (DMA) hardware external to the processor to handle high-bandwidth I/O traffic. This is discussed further in Section 11.9 on page 312. Interrupts are a form of exception and are handled as outlined below. ARM exceptions The ARM architecture supports a range of interrupts, traps and supervisor calls, all grouped under the general heading of exceptions. The general way these are handled is the same in all cases: 1. The current state is saved by copying the PC into rl4_exc and the CPSR into SPSR_exc (where exc stands for the exception type). 2. The processor operating mode is changed to the appropriate exception mode. 3. The PC is forced to a value between 0016 and 1C16, the particular value depending on the type of exception. The instruction at the location the PC is forced to (the vector address) will usually contain a branch to the exception handler. The exception handler will use rl3_exc, which will normally have been initialized to point to a dedicated stack in memory, to save some user registers for use as work registers. The return to the user program is achieved by restor...
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- Spring '09