Typical uses are a floating point fix operation which

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ises an undefined instruction trap. If a coprocessor accepts a load from coprocessor instruction, it will normally perform an operation defined by Copl and Cop2 on source operands CRn and CRm and return a 32-bit integer result to the ARM which will place it in Rd. If a coprocessor accepts a store to coprocessor instruction, it will accept a 32-bit integer from the ARM register Rd and do something with it. If the PC is specified as the destination register Rd in a load from coprocessor instruction, the top four bits of the 32-bit integer generated by the coprocessor are placed into the N, Z, C and V flags in the CPSR. Move to ARM register from coprocessor: MRC{<cond>} <CP#>, <Copl>, Rd, CRn, CRm{, Assembler format <Cop2>} Move to coprocessor from ARM register: MCR{<cond>} <Cop2>} <CP#>, <Copl>, Rd, CRn, CRm{, Examples Notes MCR MRCCS p14, p2, 3, 4, r0, r3, Cl, C2 C3, C4, 6 1. The Copl, CRn, Cop2 and CRm fields are interpreted by the coprocessor. The above interpretations are recommended to maximize compatibility with ARM development tools. 2. Where the coprocessor must perform some internal work to prepare a 32-bit value for transfer to the ARM (for example, a floating-point FIX operation has to con vert the floating-point value into its equivalent fixed-point value), this must take place before the coprocessor commits to the transfer. Therefore it will often be necessary for the coprocessor handshake to 'busy-wait' while the data is prepared. The ARM can take interrupts during the busy-wait period, and if it does get interrupted it will break off from the handshake to service the interrupt. It will probably retry the coprocessor instruction when it returns from the interrupt service routine, but it may not; the interrupt may cause a task switch, for example. Breakpoint instruction (BKPT - architecture v5T only) 141 In either case, the coprocessor must give consistent results. Therefore the preparation work carried out before the handshake commit phase must not change the coprocess...
View Full Document

This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

Ask a homework question - tutors are online