Unless the lower level models are synthesized

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Unformatted text preview: dary scan test architecture 227 Test signals The interface works with five dedicated signals which must be provided on each chip that supports the test standard: TRST is a test reset input which initializes the test interface. TCK is the test clock which controls the timing of the test interface independ ently from any system clocks. TMS is the test mode select which controls the operation of the test interface state machine. TDI is the test data input line which supplies the data to the boundary scan or instruction registers. TDO is the test data output line which carries the sampled values from the boundary scan chain and propagates data to the next chip in the serial test circuit. The normal organization of the test circuit on a board that incorporates several chips with JTAG support is to connect TRST, TCK and TMS to every chip in parallel and to connect TDO from one chip to TDI of the next in a single loop, so the board test interface has the same five signals listed above. TAP controller The operation of the test interface is controlled by the Test Access Port (TAP) controller. This is a state machine whose state transitions are controlled by TMS; the state transition diagram is shown in Figure 8.15 on page 228. All the states have two exits so the transitions can be controlled by one signal, TMS. The two main paths in the state transition diagram control the operation of a data register (DR) and the instruction register (IR). The behaviour of a particular chip is determined by the contents of the test instruction register, which can select between various different data registers: The device ID register reads out an identification number which is hard-wired into the chip. The bypass register connects TDI to TDO with a 1-clock delay to give the tester rapid access to another device in the test loop on the same board. The boundary scan register intercepts all the signals between the core logic and the pins and comprises the individual register bits which are shown as the squares connected to the core logic in Figure 8.14 on page 226. Other registers may...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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