When a cache line is replaced any dirty data is sent

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Unformatted text preview: licon The characteristics of the ARM920T are summarized in Table 12.5. Table 12.5 Process Metal layers Vdd ARM920T characteristics. 2,500,000 MIPS 23-25 mm2 Power 0-200 MHz MIPS/W 220 560 mW 390 0.25 urn Transistors 4 Core area 2.5V Clock ARM940T The ARM940T is another CPU core based on the ARM9TDMI integer core. It is simpler than the ARM920T as it does not support virtual to physical address translation. The organization of the ARM940T is shown in Figure 12.12 on page 338. The memory protection unit implements the architecture described in Section 11.4 on page 297. As the ARM940T has separate instruction and data memory ports it has two protection units, one for each of the ports. This configuration has no virtual to physical address translation mechanism. Many embedded systems do not require address translation, and as a full MMU requires significant silicon area, its omission when it is not required represents a significant cost saving. The AMBA interface and absence of address translation hardware both indicate the expectation that the application will be in embedded systems with other AMBA macrocells on the same chip. Both instruction and data caches have a size of 4 Kbytes and comprise four 1 Kbyte segments, each of which uses a fully associative CAM-RAM structure. (For an explanation of these cache terms see Section 10.3 on page 272.) They have a quad-word line structure, and always load a complete line on a cache miss if the address is cacheable as indicated by the memory protection unit. Memory protection unit ARM940T caches 338 ARM CPU Cores Figure 12.12 ARM940T organization. The caches supports lock-down, which means that sections of the cache can be loaded and then the contents protected from being flushed. Locked-down sections of the cache are clearly unavailable for further general-purpose cache use, but the ability to guarantee that certain critical code sections will always be found in the cache may be more important than getting the best cache hit rate. The caches may be locked down in 16-word units. The ARM9TDMI instruction port is used to load instructions and therefore only performs r...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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