ARM.SoC.Architecture

When this instruction is executed the only change to

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Unformatted text preview: ed or 2's-complement signed integers; the carry-in, when used, is the current value of the C bit in the CPSR. 'ADD' is simple addition, 'ADC' is add with carry, 'SUB' is subtract, 'SBC' is subtract with carry, 'RSB' is reverse subtraction and 'RSC' reverse subtract with carry. Bit-wise logical operations. These instructions perform the specified Boolean logic operation on each bit pair of the input operands, so in the first case r0[i]:= r1[i] AND r2[i] for each value of i from 0 to 31 inclusive, where r0[i] is the ith bit of r0. We have met AND, OR and XOR (here called EOR) logical operations at the hardware gate level in Section 1.2 on page 3; the final mnemonic, BIC, stands for 'bit clear' where every ' 1' in the second operand clears the corresponding bit in the first. (The 'not' operation in the assembly language comment inverts each bit of the following operand.) Register movement operations. These instructions ignore the first operand, which is omitted from the assembly language format, and simply move the second operand (possibly bit-wise inverted) to the destination. The 'MVN' mnemonic stands for 'move negated'; it leaves the result register set to the value obtained by inverting every bit in the source operand. 52 ARM Assembly Language Programming Comparison operations. These instructions do not produce a result (which is therefore omitted from the assembly language format) but just set the condition code bits (N, Z, C and V) in the CPSR according to the selected operation. CMP CMN r1, TST TEQ r1, r1, r1, r2 r2 r2 r2 , set cc on r1 - r2 ; set cc on r1 + r2 ; set cc on r1 and r2 ; set cc on r1 xor r2 The mnemonics stand for 'compare' (CMP), 'compare negated' (CMN), '(bit) test' (TST) and 'test equal' (TEQ). Immediate operands If, instead of adding two registers, we simply wish to add a constant to a register we can replace the second source operand with an immediate value, which is a literal constant, preceded by '#': ADD #1 AND #&ff r3, r8, r3, r7, ; r3 + 1 ; r8 r7[7:0] := := r3 The first example also i...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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