Writing the swi handler to start at osjg is not

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Unformatted text preview: nd operand, if it is a register, may be a logical or arithmetic shift or a rotate (see Figure 3.1 on page 54), and it may be by an amount specified either as an immediate quantity or by a fourth register. The operations that may be specified are listed in Table 5.4 on page 120. When the instruction does not require all the available operands (for instance MOV ignores Rn and CMP ignores Rd) the unused register field should be set to zero. The assembler will do this automatically. 120 The ARM Instruction Set Table 5.4 ARM data processing instructions. Opcode 124:21) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Mnemonic AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN Meaning Logical bit-wise AND Logical bit-wise exclusive OR Subtract Reverse subtract Add Add with carry Subtract with carry Reverse subtract with carry Test Test equivalence Compare Compare negated Logical bit-wise OR Move Bit clear Move negated Effect Rd:=RnANDOp2 Rd := Rn EOR Op2 Rd := Rn - Op2 Rd := Op2 - Rn Rd := Rn + Op2 Rd := Rn + Op2 + C Rd := Rn - Op2 + C - 1 Rd := Op2 - Rn + C - 1 ScconRnANDOp2 Sec on Rn EOR Op2 Sec on Rn - Op2 Sec on Rn + Op2 Rd := Rn OR Op2 Rd := Op2 Rd:=RnANDNOTOp2 Rd:=NOTOp2 11 11 These instructions allow direct control of whether or not the processor's condition codes are affected by their execution through the S bit (bit 20). When clear, the condition codes will be unchanged; when set (and Rd is not r15; see below): The N flag is set if the result is negative, otherwise it is cleared (that is, N equals bit 31 of the result). The Z flag is set if the result is zero, otherwise it is cleared. The C flag is set to the carry-out from the ALU when the operation is arithmetic (ADD, ADC, SUB, SBC, RSB, RSC, CMP, CMN) or to the carry-out from the shifter otherwise. If no shift is required, C is preserved. The V flag is preserved in non-arithmetic operations. It is set in an arithmetic operation if there is an overflow from bit 30 to bit 31 and cleared if no overflow occurs. It has significance only when an arithmetic operation has operands that are viewed as 2's complement signed values, and indicates a result that is out of range. Multiply by a constant These instructions may be used to multiply a register by a small constant much more efficiently than can be achieved using the multiply instructions described in the next section. Examples are given below. 122 The ARM In...
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