ARM.SoC.Architecture

Port two high speed uarts with an irda interface that

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Unformatted text preview: heral controllers reside, and an interface to external memory. The external memory interface presents a conventional set of signals for off-chip devices. It is similar to the AMULET2e interface (see Section 14.4 on page 384), being highly configurable and using a reference delay to time external accesses. MARBLE onChip bus External memory interface The DRACO telecommunications controller 393 Synchronous peripheral interface Figure 14.12 The AMULET3H asynchronous subsystem. Instead of using an off-chip reference delay, however, AMULETS H has an on-chip delay which can be calibrated by software against a timing reference, perhaps using a timer/counter in the synchronous peripheral subsystem for this purpose. Off-chip DRAM is supported directly, as are conventional ROM, SRAM and memory mapped peripheral devices. AMULET3H memory Organization The AMULETS processor core has separate address and data buses for instruction and data memory accesses. This would normally require separate instruction and data memories; RISC systems frequently employ a 'modified Harvard' architecture where there are separate instruction and data caches with a unified main memory. The AMULET3H controller employs direct-mapped RAM rather than cache memory as this is more cost-effective and has more deterministic behaviour for realtime applications. It also avoids separate instruction and data memories (and the associated difficulties of keeping them coherent) through the use of a dual-ported memory structure (see Figure 14.13 on page 394). Dual-porting the memory at the individual bit level would be too costly, so instead the memory is divided into eight 1 Kbyte blocks, each of which has two ports which are arbitrated internally. When concurrent data and instruction accesses are to different RAM blocks, each can proceed 394 The AMULET Asynchronous ARM Processors Figure 14.13 AMULET3H memory organization. unimpeded by the other; when they happen to conflict on the same block, one access will suffer a delay while it waits...
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This document was uploaded on 10/30/2011 for the course CSE 378 380 at SUNY Buffalo.

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