ARM.SoC.Architecture

While loops 174 draco telecommunications controller

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Unformatted text preview: mediate operands 52 implementation 86-101,201-3 adder design 87-92 barrel shifter 92-3 clocking scheme 86 control structures 99-100 coprocessor interface 101-3 datapath layout 98-9 multiplier design 93-6 register bank 96-8 In-Circuit Emulator (ICE) 207, 230, 233-6 index register 17 indirect addressing 17 initialization 10,252 initializing address pointer 56-7 input/output (I/O) 42-3, 312-15, 361 instruction cache 332 instruction decoders 99 instruction mapping 201-3 instruction register (IR) 7, 227-8 instructions 42, 105^19 breakpoint 140-1 condition codes 112 conditional execution 65, 111-13 control flow 63-8 coprocessor 135--40 count leading zeros 123-4 data operations 136-7 data processing 50-5, 82, 119-22 data transfer 55-63, 82^t, 102, 125-30, 136, 138-9 design 14-19 exceptions 108-12 execution 82-5 frequencies 166 'Halt' 383-4 load instructions 57--8 MU0 processors 8 register transfer 130-35, 139^1, 165-6 software interrupt 117-19 store instructions 57--8 SWAP instruction 309 datapath timing 86-7 Index 417 granularity 302 hierarchy 269-88 interfaces 208-16,251-2,350 mapping 222,292,312 on-chip memory 271 organization 40-1, 105-6, 393^t read-sensitive locations 312 size and speed 270,272 timing accesses 215, 385-6 see also cache memory management unit (MMU) 283-8,291, 294, 317, 345 ARM710T 321 ARM1020E 342 ARM920T 336-7 ARM940T 337 ARM MMU architecture 302-8 CP15 MMU registers 294-7, 298-302 paging 285-6 restartable instructions 287 segmentation 284-5 StrongARMSA-110 334 translation look-aside buffers (TLB) 287 virtual memory 286-7 virtual and physical caches 287--8 MIPS (Microprocessor without Interlocking Pipeline Stages) 37 MMU see memory management unit (MMU) mnemonics 111-12 modes 17 multi-user systems 291 multiple register transfer instructions 60, 129-31 multiplexers 401 multiplication 55, 93-6, 122-4, 242-3 StrongARMSA-110 332 MU0 processors 7-13 ALU design 12-13 components 7-8 control logic 10-11 datapath design 9-10 datapath operation 10 extensions 13 initialization 10 instruction set 8 logic design 8-9 register transfer level design 10 mutual exclusion 309 N-Trace 239 NaN (Not a Number) 160 NAND 4-5, 399^(00 never condition (NV) 111 non re-entrant code 178-9 normalized numbers 159,160 number of addresses 14-16 numbers 153, 155-6 binary numbers 400--1 floating-point 158-63 ranges 154-5 Oak DSP core 352-3 on-chip debug 261 on-chip memory 271 OneCVWS22100 GSM chip 352-5 Open Microprocessor systems Initiative (OMI) 397 operands 50-3, 168-9 op...
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