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Unformatted text preview: RF IF
The World Leader in HighPerformance Signal Processing Solutions RF Power Amplifiers
May 7, 2003 RF IF Outline
PA Introduction
Power transfer characteristics Intrinsic PA metrics Linear and Nonlinear amplifiers PA Architectures SingleStage Linear PA
Loadline theory Transistors size Input and Output Matching So why is this so hard? Highefficiency PAs
Class A, AB, B and C amplifiers
2 RF IF Outline (cont.)
RealWorld Design Example
Selecting architecture, number of stages Designing stages Tuning: interstage match and output System specifications
Ruggedness: load mismatch and VSWR Linearity: spectral mask (ACPR), switching transients Noise in receive band Power Control 3 RF IF PA Transfer characteristics Defining linearity:
Pout (dBm)
linear nonlinear (actual) 1
G Pout = Pin + G
0 Pin (dBm) 4 RF IF PA Transfer characteristics Defining linearity:
Pout (dBm) Gain (dB)
PMAX P1dB 1 G Pin (dBm)
5 RF IF PA Introduction: Intrinsic PA Metrics
P1dB: Output power at which linear gain has compressed by 1dB (measure of linear power handling) PMAX: Maximum output power (saturated power) Gain: Generally taken to mean transducer gain Power delivered to load Power available from source
PAE: Poweradded Efficiency Power to load Power from source Power from supply
6 RF IF Linear and Nonlinear PAs
"Linear PA" generally refers to a PA which operates at constant gain, needs to preserve amplitude information
POUT (dBm) Designed to operate here
PIN (dBm) Not necessarily class A (will discuss later ...) Peak efficiencies often only 40 to 45 % Useful for modulation schemes with amplitude modulation (QPSK, 8PSK, QAM)
7 RF IF Linear and Nonlinear PAs
"Nonlinear PA" generally refers to a PA designed to operate with constant PIN, output power varies by changing gain
Designed to operate here: NOT fixed gain! POUT adjusted through bias control
PIN (dBm) POUT (dBm) 8 Operation in saturated mode leads to high peak efficiencies > 50%; "backedoff" efficiencies drop quickly Useful for constantenvelope modulation schemes (GMSK) RF IF PA Architectures
Typical 2stage (6.012) design
VPOS 50 IREF input 50 Max power transfer? VB1
9 VB2 RF IF PA Architectures
Typical 2stage RF PA design
VPOS
inductive RF choke allows output to rise above VPOS, doesn't dissipate power
matching network matching network RF input 50 May require additional RF choke here to isolate input from bias circuit L's and C's to transform load impedance VB1
10 VB2 RF IF PA Architectures
Typical 2stage RF PA design
VPOS
Additional caps may be required for matching network, harmonic termination matching network matching network RF input 50 VB1
11 VB2 RF IF PA Architectures
Typical 2stage RF PA design
VPOS matching network RF input matching network 50 bond wires (at least ...) VB1
12 VB2 RF IF PA Architectures
Typical 2stage RF PA design
VPOS matching network RF input matching network 50 VB1
13 VB2
Consider this ... RF IF PA Architectures
"Gain stage" is one transistor with passive elements "Active" components often limited to 2 or 3 transistors (gain stages) in signal path Transistor design very important!
Many parallel transistors often look like minicircuits themselves Passive components just as important as transistors!
Circuits must be tunable to account for uncertainties in determining values a priori (i.e. simulations stink especially largesignal, RF simulations) Q and parasitic elements of passives important 14 RF IF SingleStage Linear PA
Loadline theory: the maximum power that a given transistor can deliver is determined by the power supply voltage and the maximum current of the transistor ID or IC (mA/mm) IMAX RLOAD,opt. 2VPOS / IMAX 2*VPOS VDS or VCE (V)
15 RF IF SingleStage Linear PA
Transistor size chosen to deliver required output power POUT IMAXVPOS / 4
ID or IC (mA/mm) RL,opt. IMAX Quiescent point: Class A IMAX/2, VPOS VDS or VCE (V)
16 2*VPOS RF IF SingleStage, Linear PA
Design output match to transform 50 load to RL,opt at transistor output; then design input match for gain (complex conjugate) V
POS input match
CJC output match 50 VB1
17 RF IF Seems simple, so why is this so hard?
Determining IMAX is not so easy
For BJTs, one reference suggested that "the best way of estimating its value is to build an optimized class A amplifier and observe the dc supply current."1 Somewhat easier for depletionmode GaAs FETs IMAX often corresponds to VGS = 0V Values don't scale linearly with transistor size Optimal load resistance only a theoretical number
Transmission line effects, parasitic L's and C's significant at RF Common practice is to vary the load of an actual transistor to determine the peak output power: the loadpull measurement (Noticing a distinct pattern of "empirical" design emerging?)
1 RF Power Amplifiers for Wireless Communications, Steve Cripps, Artech House, Boston, 1999. 18 RF IF Seems simple, so why is this so hard?
Now consider the problem for multiple stages ... double the trouble
Typical singlestage gain only 10 15 dB Interstage match now required to match input impedance of 2nd stage to desired output impedance of 1st stage. Problems with matching circuits:
Large matching ratios high Q circuits for simple L matches Multisegment matches use valuable real estate, add cost Transistor itself maters a lot!
Many parallel transistor Ballasting, balancing and layout extremely important 19 RF IF Highefficiency PAs
Input signal swing turns on transistor conduction for only part of sinusoidal period ID or IC (mA/mm) IMAX Class A Quiescent point: Class AB to B VDS or VCE (V) 20 RF IF HighEfficiency PAs Conduction Angle: = 2 Class A: Class AB: Class B: ID or IC ID or IC 2 3 t < < 2
3 t ID or IC 2 = 2 3 t Class C: < 21 RF IF HighEfficiency PAs
Assume output match will filter out nonlinearities caused by discontinuous conduction: input match output match 50 50 transformed to RL,opt: All harmonics filtered out VB1
22 RF IF HighEfficiency PAs
If all harmonics filtered out, then voltage output at load is a pure sinusoid, despite discontinuous conduction
VOUT IMAX 2 3 t IC 2 3 t Energy stored in reactive elements delivers current to the load during transistor offportion of cycle
23 RF IF HighEfficiency PAs
Now consider peak efficiencies Calculate fundamental component of current* Idc = (1/2) In =
IMAX /2 (1/)  /2 Ipk cos(t) cos(nt) dt
Ipk = IMAX  IQ  /2 /2 IQ + Ipk cos(t) dt IC
IQ /2 2 t * There are many texts which cover reducedconduction angle calculations. See for example Principles Of Power Electronics, Kassakian, Schelcht and Verghese, Ch. 3. 24 RF IF HighEfficiency PAs
From phasor plot: cos(/2) =  IQ / Ipk =  IQ / (IMAX IQ) Put it all together and do the math, you get: Idc = IMAX 2 2sin(/2) cos(/2) IMAX 2 1 cos(/2) sin 1 cos(/2) I1,0p = Assume VOUT the same for all classes: V1,0p = VPOS
25 RF IF HighEfficiency PAs
Summary of PA "ideal" peak efficiencies Class A: Class B: Class C: P1 Pdc P1 Pdc = = (IMAX /2) /2 VPOS /2 (IMAX /2) VPOS (IMAX /2) /2 VPOS /2 (IMAX /) VPOS = 50 % = 78 % Ideally can go to 100%, but P1 drops steadily beyond =, goes to 0 at 100%! 26 RF IF HighEfficiency PAs
What happened to our load line?
For class B fundamental RL,opt = VPOS/(IMAX/2) Didn't change ID or IC (mA/mm) IMAX Class A ?
VPOS 2VPOS Class B is here!
27 VDS or VCE (V) RF IF HighEfficiency PAs
What happened to our load line?
For class B fundamental RL,opt = VPOS/(IMAX/2) Didn't change ID or IC (mA/mm) quasistatic
IMAX Class A
IMAX /2 In quasistatic picture, resistance presented to transistor output cut in half. But average resistance is the same for class A VPOS 2VPOS Class B is here!
28 VDS or VCE (V) RF IF HighEfficiency PAs
Now consider "linearity"
Clearly the current waveforms are far from linear BUT ...
Overall POUT vs. PIN transfer function can still be quite linear, especially for true Class B where output current waveform is symmetrical with respect to input waveform ID or IC 2 3
t Because conduction angle is constant, POUT changes proportional to PIN
29 RF IF RealWorld Design Example
IDEAL: Design each stage independently
Determine required gain number of stages Determine POUT for each stage Determine RL,opt for each stage Determine input impedance for each stage Design matching networks for interstage, load and input REALITY:
IMAX doesn't scale nicely with transistor size. Without good IMAX numbers, can't determine RL,opt. Need to do loadpull. Even load pull measurements have limited accuracy for very large transistors Designs are very empirically driven!
30 RF IF RealWorld Design Example GSM 900 MHz, GaAs HBT PA Design
POUT = 33 dBm (linear) = 2 W VCC = 3.5V RLOAD = VCC2 / 2*POUT = 3 IMAX = 2*VCC /RLOAD = 2.33 A (Note: expect saturated power to be ~ 35 dBm) Input power: constantenvelope +5 dBm Gain = POUT PIN = 27 dB. Expect roughly 10 dB per stage 3 STAGE DESIGN
31 RF IF RealWorld Design Example
Stage 1: Gain = 10 dB POUT = 15 dBm
RL1 = VCC2 / 2*POUT = 194 IMAX = 2*VCC /RLOAD = 36 mA Chose class A: IDC = IMAX/2 = 18 mA (18 mA insignificant compared to 2.33 A) Stage 2: Gain = 10 dB POUT = 25 dBm
RL2 = 19.4 IMAX = 360 mA Still probably class A (maybe AB): IDC = IMAX/2 = 180 mA Stage 3: Gain = 7 dB POUT = 33 dBm
RL2 = 3 , IMAX = 2.33 A Class B: IDC = IMAX/ = 742 mA
32 RF IF RealWorld Design Example A note on "Gain"
Taking a very simplistic view of common emitter stages:
gm1 = IC / VTh = 18 mA / 0.025 V = 0.696 S gm1RL1 = 0.696 194 = 135 NOT 10 dB! BUT ...
re1 = 1/gm1 = 1.44 re2 = 1/gm2 = 0.144 re3 = 1/gm3 = 0.035 1. Remember it's power gain, not voltage gain. Can lose voltage at input match. 2. It's pretty tough not to get significant degeneration!
33 RF IF RealWorld Design Example
Efficiency calculations: IDC1 = 18 mA, IDC2 = 180 mA, IDC3 = 742 mA Total DC Current: 940 mA P1 Pdc (IMAX /2) /2 VPOS /2 IDCVPOS = = 62 % Realistically may get as high as 55% 34 RF IF RealWorld Design Example: LoadPull
After initial "guesses" at transistor sizes, loadpull to determine actual target load for matching circuits
Load pull: Vary ZL Plot contours of constant power RF input ZL
PMAX PMAX 1dB PMAX 2dB VB
35 RF IF RealWorld Design Example: Loadpull Notes on loadpulling:
Most accurate on probe station, but insertion loss of probes prevents it from being useful for large transistors ("Insertion loss" is RF code word for resistance) Bonded devices on evaluation board must be carefully deembedded Even using electronic tuners, accuracy is poor for very large transistor (i.e. for loads in the 2 5 range) 36 RF IF RealWorld Design Example: The Circuit
VPOS GaAs die
RF input 50 VB1
37 VB2 VB2 RF IF RealWorld Design Example: The Circuit
VPOS Interstage match
RF input 50 VB1
38 VB2 VB2 RF IF RealWorld Design Example
VPOS
printed inductor LBOND + TL RF input LBOND + TL LBOND 50 Lparasitic + LVIA VB1
39 VB2
LBOND + LVIA VB2 RF IF RealWorld Design Example
VPOS may need to add feedback for stability RF input 50 VB1
40 VB2 VB2 RF IF RealWorld Design Example: Tuning
Example of interstage match, 1st to 2nd stage RL1 = 194 (?) Both are really ZIN2 = 30 j10 (?) just guesses Transmission line Bond wire RL1 * Go to Winsmith: test
41 ZIN2 RF IF RealWorld Design Example: Tuning
Example of interstage match, 2nd to 3rd stage RL2 = 19.4 ZIN3 = 2 j2 Transmission line Bond wire RL2 * Go to Winsmith: test2
42 Offchip ZIN3 Bond wires RF IF System Specifications
Ruggedness
50 load is for antenna in free space. Place antenna on a metal plate and can easily get VSWR of 4:1 Typical PA specs are: don't oscillate at up to 4:1, survive up to 10:1 (!) V1 = V1+ V1 t = t1 V1+ V1 z V1 t t = t2 43 RF IF System Specifications
Linearity
For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important raised cosine filter Power Spectral Density (PSD) ch. B ch. C (dBm/Hz) ch. A fcf
44 fc fc+f RF IF System Specifications
Linearity
For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important 3rd order distortion Power Spectral Density (PSD) ch. B ch. C (dBm/Hz) ch. A fcf
45 fc fc+f RF IF System Specifications
Linearity
For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important Power Spectral Density (PSD) (dBm/Hz) ch. B
5th order 3rd order distortion distortion ch. A ch. C
th 3rd order 5 order distortion distortion fcf
46 fc fc+f RF IF System Specifications
Linearity
For linear PAs, Adjacent Channel Power Ratio (ACPR) is very important f
30 kHz Power Spectral Density (PSD) ACPR =
(dBm/Hz) Pwr. Ch. B Pwr. Ch. A fcf
47 fc fc+f RF IF System Specifications
Linearity
For nonlinear PA in TDMA systems, harmonic spurs and switching transients are most common measure of linearity POUT (dBm) 577s GSM burst Signal ramping profile must fall within time mask time
48 RF IF System Specifications
Noise in receive band:
Obvious spec. in systems where Tx and Rx are operating at the same time (FDD) 30 kHz 30 kHz Power Spectral Density (PSD) (dBm/Hz) 45 MHz Tx
49 Rx RF IF System Specifications
Noise in receive band:
Obvious spec. in systems where Tx and Rx are operating at the same time (FDD) Not so obvious spec in TDD system. Problem primarily of mixing by the PA (22 1 or 2 1 ) Power Spectral Density (PSD) (dBm/Hz) 45 MHz Tx
50 Rx RF IF Power Control
For linear PA, expected to operate at constant gain. Power control is therefore a function of PIN. Role of bias circuitry is to maintain constant gain over PIN, temperature (PTAT?). Power transistor 51 RF IF Power Control
For nonlinear PA, expected to operate at constant PIN. Power control is achieved by varying gain. External control signal VAPC Onchip bias circuitry Power transistor 52 ...
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This note was uploaded on 10/29/2011 for the course EE 6.976 taught by Professor Michaelperrott during the Spring '03 term at MIT.
 Spring '03
 MICHAELPERROTT
 Amplifier, Signal Processing

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